LQ14F040001), the National Natural Science Foundation of China (Nos. Veeam Backup & Replication Supported Environments. Project supported by the Zhejiang Provincial Natural Science Foundation of China (No. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%. Click Here for Sample Image Purchase Sample Jar Digital swatches are a rough estimation of color. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. Lime Wash Light gray simple gray that runs a bit cooler. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. As a result, the switch power caused by unnecessary discharging of the bit line is reduced. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. Thus, the word line can be opened and shut off in time. In the novel design, the delay of word line enable and disable paths are balanced. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. A design of a replica bit line control circuit to optimize power for SRAM is proposed.
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